The present invention relates to a method and/or architecture for implementing an address compare generally and, more particularly, to a method and/or architecture for implementing a wired AND (or wired OR) address compare.
Conventional address compare circuitry uses standard two and three input logic gates to AND two addresses together. Such conventional approaches use silicon area inefficiently and require a large amount of routing, particularly for a large register. The AC power drawn by such conventional circuits is due to the larger gate area switched on each clock cycle.
The present invention concerns an apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output it signals are generally each at either (i) the same logic state or (ii) a don""t care state.
The objects, features and advantages of the present invention include providing a method and/or architecture for an address compare circuit that may (i) reduce routing requirements of compare circuits, (ii) provide reduced logic complexity, (iii) reduced die area, (iv) reduce routing and switching gate capacitance, (v) lower current consumption (ICC), and/or (vi) eliminate or reduce DC power consumption.